China is about to have the ability to make 5 Nm chips, although it faces a difficult solution problem

SMIC (Semiconductor manufacturing international corp), the largest Chinese semiconductor manufacturer has been working on the development of Your own 5 nm photolithography. In early February 2024 the newspaper Financial Times He said he had access to two experts in the integrated circuit industry who defended that this company was finalizing the refinement of their semiconductor manufacturing processes in their machines deep ultraviolet lithography (UVP).

Its purpose was to have the necessary technology to make 5 Nm chips massively before the end of 2024, although it did not succeed. If its 5 Nm chips had already been successful in this project, the first Huawei devices or any other SMIC client equipped with this type of integrated circuits would have even seen the market. Be that as it seems, now, this technology is ready.

The challenge facing SMIC is the performance by wafer

According to Dr. Kiman expert in the manufacture of integrated circuits who has worked in Samsung and who currently investigates for TSMC in the US, SMIC is about to start the production of 5 Nm chips. It is perfectly credible because, as we have just seen, we know with certainty that this company has been working on this technology for several years. And, in addition, Dr. Kim is a reliable source. However, this expert has pointed out something crucial that we should not overlook: the performance per wafer that SMIC has currently achieved in its 5 Nm nodes is less than 30%.

When semiconductor manufacturers produce a chip wafer, some of those nuclei do not work properly. It is normal. When they launch a new lithographic node, their performance by wafer usually has a margin of broad improvement, but little by little, as engineers refine their integration processes, This parameter improves. A mature lithography can deliver to integrated circuit manufacturers a very high performance, but an incipient technology usually moves in the orbit of 50% performance, so only half of the chips produced work correctly.

The problem is that for an integration technology to be profitable from an economic point of view, its performance by wafer has to be At least 70%. And, as we have just seen, Dr. Kim argues that the SMIC 5 NM node is below 30%. It is objectively a very poor performance, but we know what this low figure explains: the technique used by this manufacturer to produce these semiconductors. It is known as Multiple patterningand SMIC has used it for more than a year and a half to make 7 NM chips for Huawei and other customers.

This strategy consists in transferring the pattern to the wafer in several passes with the purpose of increasing the resolution of the lithographic process. It works, but is responsible for wafer performance is clearly improvable. SMIC engineers have been forced to resort to Multiple patterning because The US and Netherlands sanctions They prevent Asml from selling their extreme ultraviolet lithography equipment to their Chinese customers, which are the ideal to make chips of 7 nm or less.

With the UVP machines that SMIC has, it will be very difficult for wafer performance to be optimal, so in all 5 Nm integrated circuits they will be scarce and expensive. The definitive solution to this problem for SMIC, Huawei and the other Chinese companies that are dedicated to semiconductors inevitably goes through developing their own UVE lithography teams. They are in it.

Image | SMIC

More information | Dr. Kim

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