There is an indispensable component to the semiconductor industry that often goes unnoticed: the software used to Design cutting-edge integrated circuitsknown as EDA by its English name (Electronic Design Automation or automation of electronic design). It is currently in the hands almost exclusively of US controlled companies and its allies, so China needs to have its own software tools specialized in chip design. And little by little he is having them.
One of the Chinese companies that are already working in this area is SEIDAand, curiously, its leader knows the American idiosyncrasy very well. Liguo “Recoo” Zhang is Chinese, but he has lived in the US for several decades and has worked at Siemens EDA, the US subsidiary of this German company that dominates the chip design software market in China. SEIDA promised to have its OPC software ready (Optical Proximity Correction or optical proximity correction) by early 2024, but has since disappeared from the news radar.
OPC software is very important because it corrects in advance the optical distortions that occur during the photolithography process. When ultraviolet light is shined onto a silicon wafer to “print” the chip design, the light diffracts and the resulting shapes are not exactly as designed. Edges are rounded, corners are deformed and fine lines are narrowed. OPC software anticipates and compensates for these distortions by modifying the original design before it reaches the lithography machine. In this way, the final result on the wafer conforms to the intended design.
The EDA that changes the rules
In October 2025 Qiyunfang, a subsidiary company of YesCarrier and Huawei, advertisement that your EDA tools They were already being used by more than 20,000 engineers in China. This data has not been independently verified, so it is most prudent to collect it with some reservations. In any case, SEIDA and Qiyunfang are not the only assets that China has in the field of integrated circuit design software.
LogicFolding architecture folds transistor-level logic within a single chip into multiple vertical layers
And a group of researchers from Peking University has presented a prototype of an EDA tool that is compatible with Huawei’s LogicFolding architecture. The goal of the latter company is to produce chips by 2031 capable of matching the performance of 1.4nm integration technology from TSMC, Intel or Samsung, but without depending at any time on Western chip manufacturing tools subject to US export restrictions.
The LogicFolding architecture folds transistor-level logic within a single chip into multiple vertical layers. This optimization requires the use of location and routing tools capable of working on the entire vertical structure simultaneously, instead of working on separate layers. Peking University addresses this problem precisely because its prototype treats the multi-layer structure as a unified design space from the beginning, as opposed to conventional designs, in which each layer is optimized separately and then stacked.
During initial testing with industrial-grade open source integrated circuits, this EDA tool has achieved, according to its designersreduce the total length of internal wiring by 30%. Besides, has introduced performance improvements and thermal management versus conventional EDA workflows. It doesn’t look bad, but we will have to wait until Huawei places its first commercial chips with LogicFolding architecture on the market to assess whether this technology is really up to the task. This company has anticipated that its next generation of Kirin chips, arriving this fall, will be the first to incorporate these innovations.
Image | YesCarrier
More information | SCMP
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