It has been a long time since we witnessed a milestone like this. Innovations in the field of semiconductor manufacturing they happen constantlybut what IBM has just announced is a monumental achievement: it has managed to produce the world’s first chip with subnanometer technology. This simply means that it has been manufactured on a 0.7 nm (or 7 angstroms) node, which has allowed this company’s engineers to pack almost 100 billion transistors into a surface the size of a fingernail.
Crossing the nanometer barrier is not just a matter of numbers. For decades, the integrated circuit industry has evolved under the logic of Moore’s Law. The problem is that this principle has been losing force as transistors approach the dimensions of the atoms themselves. Quantum physics is relentless: each further reduction is an almost unsolvable problem. Reaching 0.7 nm means that IBM has found a way out of that alley. And it has done so not by further miniaturizing transistors according to conventional designs, but by completely reinventing how they are built.
This new chip offers up to 50% more performance. Or 70% more energy efficiency if we compare it with 2nm integrated circuits from IBM itself. These two metrics represent the extremes of a spectrum that designers can adjust depending on the application these semiconductors are intended for. For workloads of artificial intelligence (generative AI), cloud infrastructure or next-generation devices, this flexibility is not a minor detail: it is exactly what differentiates a viable chip from a disruptive one.
Stack to scale
The most important innovation of IBM’s 0.7nm integrated circuit is the technology nanostackwhich we can translate into Spanish as ‘nanostacking’. This is the industry’s first three-dimensional architecture based on stacked nanosheets, and has been developed entirely by IBM.
To understand what it means, we are interested in remembering that the previous generation of frontier technology, nanosheets, represented a very important conceptual leap compared to FinFET transistors: instead of a transistor with a vertical fin, nanosheets have several horizontal sheets of silicon stacked and wrapped around the control gate, which improves electrical performance in a smaller space.
Nanostack goes one step further: it stacks and staggers entire transistors in three dimensions, thus taking advantage of 3D sequential integration to insert more logic in less surface. What differentiates this architecture from a mere exercise in miniaturization is that each stacked layer can incorporate combinations of different materials, allowing the performance and energy efficiency of each transistor to be optimized independently.
Not all transistors on a chip need to behave the same. Some prioritize speed, and others prioritize energy savings
Or put another way: not all transistors on a chip need to behave the same. Some prioritize speed, and others prioritize energy savings. Nanostack makes it possible to fine-tune that balance layer by layer, something that planar architectures (or even conventional nanosheets) do not allow with the same granularity.
IBM also presented results at the VLSI 2026 conference that demonstrate a 40% improvement in SRAM scaling thanks to this architecture, enabling the manufacturing of semiconductors capable of handling the bandwidth demands of the most demanding AI workloads.
Experimental validation of the architecture nanostack It is based on three essential pillars: the ultra-thin dielectric link in CMOS integration, the demonstration of dual-channel engineering capability and the functional operation of a CMOS inverter with expected switching performance.
This last point is especially important: a functional CMOS inverter is, in practice, the most basic logic unit of any digital circuit. That nanostack Running it with the expected metrics confirms that this architecture is not just a promising lab result; It is a technology that can be physically built and translated into real computing.
IBM and its partners (Lam Research, Tokyo Electron and SCREEN Semiconductor Solutions) have long been working on manufacturing tools and processes with High NA extreme ultraviolet lithography of ASML at its facilities in Albany (New York).
Anderon is a quantum chip manufacturing company independent of IBM
However, traveling the path that separates the laboratory from the factories requires a lot of time. IBM estimates a production horizon of between three and five years for the first commercial adoption of the technology nanostack in the sub-nanometer node, with a schedule that projects at least a decade of additional scaling.
On the other hand, this company has just announced Anderon, a quantum chip manufacturing company independent of IBM that will combine its experience in quantum computing and semiconductors to manufacture quantum wafers on an industrial scale.
Be that as it may, with the 7 angstrom node IBM not only demonstrates that the era of subnanometer scaling is physically possible: It also claims its role as a reference laboratory in an industry that has been searching for a way out of the limits of silicon for years.
Image | IBM
In Xataka | An unexpected salvation for the end user emerges from the memory market debacle: Chinese chips
In Xataka | China needs to develop a new type of chips immune to US sanctions. And your scientists have just achieved it
GIPHY App Key not set. Please check settings