The IMEC laboratory has found a way to extend the life of silicon

IMEC just updated your semiconductor journey and the fact that attracts the most attention is a date: 2038. That is the year in which, according to this Belgian research center, the industry will begin the production of class 3 angstrom integrated circuits (0.3 nanometers). This is not the first time we have talked about this milestone; a little over a year ago We analyze in Xataka a slide from IMEC that placed this leap in 2035. The new forecast delays it by three years, but in exchange it gives us something much more valuable: how to get there.

And to reach 0.3 nm it is not enough to improve photolithography alone. IMEC states that the contact poly pitchwhich is the minimum distance between transistors that for decades has been the main indicator of technological progress, will no longer be significantly reduced starting with the A10 generation, which is scheduled for 2030 or 2031. From then on, to increase density it will no longer be enough to shrink the transistors; They will have to be stacked. This paradigm shift has its own name: CFET transistors (Complementary FET).

This strategy is not new, although until now it was a distant promise. And the interesting thing is that the IMEC itinerary gives it a date, context, and connects directly with everything we have explained in our articles dedicated to IT teams. UVE Hyper-NA photolithography. These machines will be needed to manufacture these chips, although they are still being developed by ASML.

Why CFET technology is going to retire GAA transistors

The transistors Gate-All-Around (GAA), which the semiconductor industry began to adopt massively in the 2nm generationthey still have a journey. IMEC estimates that this architecture will remain viable until the A10 generation, which will arrive in 2030 or 2031, giving it a useful life of about seven years from its introduction. It is a reasonable period of time if we compare it with previous generations of transistors, but the Belgian research center already makes it clear that it has an expiration date.

The underlying problem is geometric. The GAA transistors improved the electrostatic control of the channel by completely surrounding it with the gate, but they still placed the type materials n and p one next to the other, in the horizontal plane. This provision has an obvious physical limit: There will come a time when it will no longer be possible to continue reducing the distance between them without compromising the electrical performance of the chip. This is precisely what will begin to happen when the A10 generation arrives, according to IMEC.

CFET transistors solve this problem by stacking the type material n directly above type pvertically. IMEC’s ​​itinerary places their arrival as firm candidates for chip production in the A7 generation, which is scheduled for 2033. And, in addition, it explicitly associates them with the need to resort to power delivery systems on the back side of the wafer, which IMEC considers mandatory in this architecture. From there, the itinerary itself anticipates an evolution in two phases: first the sequential CFET technology will arrive, and later the united CFET structures, already in the A3 generation of 2038.

The most interesting thing about this approach is that it changes the meaning of the Moore’s Law. IMEC recognizes that the contact poly pitch It will barely move between the A10 and A5 generations. Carry stuck at 42nm for several years. The density gains that we traditionally measured in individual transistor nanometers now depend on the height of the cell and how many layers can be stacked vertically. It is, in a way, a confession: horizontal scaling is exhausted, but the industry has found a third dimension in which it can continue growing.

Image | Samsung

More information | Tom’s Hardware

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