The development of current semiconductor technology is deeply dependent on the size of the transistors that reside within the chips. TSMC, Intel, Samsung and other integrated circuit manufacturers they dedicate a lot of resources generation after generation of its technologies to the optimization and the miniaturization of its transistors. Even so, perfecting them is so difficult that sometimes they barely manage to improve them between two generations of consecutive integration technologies.
That the chip industry depends so deeply on transistor size is a problem. Make them smaller it’s getting harderso the ideal is to undo this dependency as much as possible with a purpose: to ensure that the integration technologies developed by integrated circuit manufacturers continue to improve without being so profoundly limited by the physical characteristics of the transistors.
This is precisely what Huawei has just achieved as part of the effort that China is making to ensure the development of its chip industry despite the pressure of US sanctions. He Tingbo, the president of the semiconductor business and director of the scientific committee of this company, has presented a new scaling law and a new chip architecture capable, on paper, of taking its semiconductors to a lithographic process node equivalent to 1.4 nm by 2031. Currently the most advanced integrated circuits that TSMC, Intel or Samsung produce are 2 nm.
The “tau scaling law” promises
He Tingbo made this announcement during his keynote address at the IEEE International Symposium on Circuits and Systems (ISCAS 2026) in Shanghai, China, today. Huawei’s plan is to continue improving the performance and density of its chips despite restrictions that limit China’s access to the most advanced semiconductor manufacturing equipment. And the heart of their strategy is the “tau scaling law.”
Tau is the time it takes for electrical signals to go from one transistor to another. Huawei’s bet is to reduce it to the maximum
This principle seeks to reduce the time it takes for signals and data to travel through computer chips and equipment. According to He Tingbo, it proposes a paradigm shift that replaces the traditional geometric miniaturization of transistors. for a temporary escalation (τ), hence its name. It seems like a very complicated strategy, but it’s actually reasonably simple.
We can easily understand what it is by referring to this example. Let’s imagine that we have a city (the chip) with many buildings (transistors) connected by roads (wires). Moore’s Law says: “make buildings smaller to fit more into the same space.” Huawei, however, proposes: “buildings can no longer be much smaller, so instead let’s make cars (electric signals) travel faster on the roads, and redesign the urban layout so that they travel less distance.” τ (tau) is, precisely, the time it takes a car to go from one building to another, and Huawei’s commitment is to reduce it as much as possible.
Huawei’s LogicFolding architecture plays an essential role in this approach. And, if we continue with our example, it proposes a new design of the roads on which cars circulate, so that the chip will perform better without the need to build smaller buildings. Huawei has anticipated that its next generation of Kirin chips, which will arrive next fall, will be the first to implement the LogicFolding architecture.
Image | TSMC
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